Students in US. may have chance to fabricate their chip through MOSIS without any charge for research or study purpose. For those new IC designers, they may not be clear about the procedure to submit the design to MOSIS. Here is several tips for the college students. The original version is contributed by Xiaowen Liu and finalized by Haitao Li from AMSaC lab at Michigan State University. In this article, the IC design tool is Cadence and the operating system is Unix\Linux. The layout file is in GDS format and submitted through FTP. You may also refer to this link for MOSIS submition: http://cmosedu.com/cmos1/mosis/mosis.htm
1. Official submission steps chart: A MOSIS offical chart to submit a design is available here: http://www.mosis.com/support/submit/. However, several details are lacked here. Therefore, you may need the tips in this article.
2. DRC&LVS: To prepare to submit you design to MOSIS, your design should have no DRC and LVS errors. After that, streaming out you design in GDS format (the steps is not the point in this article). To verify that the output GDS file has no error, create a new cadence library and stream in that file. Run DRC and LVS to check whether there is any error available.
3. New design project of MOSIS: As a college student, you need to contact with the professor in your college having the permission to create a new design project of MOSIS. If there is no professor in charge of that, you need to request one to submit a request to MOSIS for that permission. When the professor create the new project of MOSIS, several information may be needed. Check this new project form here for details. Luckily we can update most the information with another update form in the future. After the creation of the new project form, you will obtain a design number and a password, which is really important for the layout submission.
4. CRC check: A program needs to be run for layout GDS file CRC check. The program is here. Two versions are available. For windows version, don’t double click it. Instead, run it under DOS mode (switch to it with keys of “start+R”). Run it by “mosiscrc filename.gds”. Two numbers are generated for final layout submission. For C source code version, run command “gcc mosiscrc.c -o mosiscrc” to compile it to executable program. Run “mosiscrc -b xx.gds” to get two CRC check numbers.
5. Fabrication form: Fill out the fabrication form with your project number and password. Here you need also to provide the two CRC check numbers. [Update] The easiest way to submit a layout file is through https. If you want to submit through FTP, here you need to provide the FTP host name. For example, the FTP host we usually use at MSU is a unix sever with name of “scully DOT egr DOT msu DOT edu”.
6. Layout submission:[Update] The easiest way to submit a layout file is through https. You will get a update link. If you choose to upload through FTP, you need to do the following things:
Login the FTP host you filled out in the fabrication form. Here we take ”scully DOT egr DOT msu DOT edu” and use Unix system for example.
[1] Open a new terminal and type in “ssh -X FTPhostname”.
[2] Type in “ftp ftp.design.mosis.org”.
[3] Type in your design number, such as 80000 (go back to tip 3 for this number) and password you created in fabrication form.
[4] Type in “binary”.
[5] Type in “put xxx.gds”
[6] Type in “bye”.
Note that after typing in “put xxx.gds”, the GDS layout file starts to tranfer to MOSIS site. If the following information shows such as”4552704 bytes sent in 14 seconds”, it means that the FTP transfer is successful.
7. Not far from party time. You will get an Email from MOSIS to notice that the design status is “queued for fabracation”. You can also login the MOSIS project system through this link to check the design status. As long as you get this message, go directly to tip 9! However, if you find that a new layout file need to be submitted. Following tip 8.
8. Layout file re-submission: Cancel the former fabrication form with this form, and then following tips 5-7 to submit your new layout file.
9. Party time! IC design especially the analog IC design may make you very tired after your chip submission. The work may let you step away from your friends and family for a period. Therefore, spend some time to relax yourself and stay with you family and friends. Have a party and take a rest! Good luck for your chip!
